View AD8331-EVAL_1442061.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ultralow noise vgas with preamplifier and programmable r in ad8331/ad8332 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved. features ultralow noise preamplifier voltage noise = 0.74 nv/hz current noise = 2.5 pa/hz 3 db bandwidth: 120 mhz low power: 125 mw/channel wide gain range with programmable postamp C4.5 db to +43.5 db +7.5 db to +55.5 db low output-referred noise: 48 nv/hz typical active input impedance matching optimized for 10-/12-bit adcs selectable output clamping level single 5 v supply operation available in space-saving chip scale package applications ultrasound and sonar time-gain control high performance agc systems i/q signal processing high speed dual adc driver general description the ad8331/ad8332 are single- and dual-channel ultralow noise, linear-in-db, variable gain amplifiers. although optimized for ultrasound systems, they are usable as low noise variable gain elements at frequencies up to 120 mhz. each channel consists of an ultralow noise preamplifier (lna), an x-amp? vga with 48 db of gain range, and a selectable gain postamplifier with adjustable output limiting. the lna gain is 19 db with a single-ended input and differential outputs capable of accurate, programmable active input impedance matching by selecting an external feedback resistor. active impedance control optimizes noise performance for applications that benefit from input matching. the 48 db gain range of the vga makes these devices suitable for a variety of applications. excellent bandwidth uniformity is maintained across the entire range. the gain control interface provides precise linear-in-db scaling of 50 db/v for control voltages between 40 mv and 1 v. factory trim ensures excellent part-to-part and channel-to-channel gain matching. differential signal paths lead to superb second and third order distortion performance and low crosstalk. functional block diagram bias and interpolator vol1 vpsv voh1 v mid bias (v mid ) com1 lna 1 vga 1 ? + ? + ? + [(?48 to 0) + 21] db ? + lna 2 vga 2 post amp1 post amp2 enb vps1 26 23 27 28 1 2 3 6 com2 inh2 lmd2 inh1 lmd1 vps2 vin1 vip1 lop1 lon1 vin2 vip2 lop2 lon2 gain int vol2 voh2 gain clamp rclmp comm hilo vcm2 vcm1 3.5db/15.5db +19db 25 24 22 21 15 20 9 19 4 5 7 8 14 18 11 17 16 10 13 12 03199-b-001 figure 1. ad8332 shown 28-lead tssop g a i n ( d b ) frequency (hz) ?10 0 10 20 40 30 50 100k ?20 1m 1g 100m 10m v gain = 1v 0.8v 0.6v 0.4v 0.2v 0v 03199-c-002 figure 2. frequency response vs. gain the vgas low output-referred noise is advantageous in driving high speed differential adcs. the gain of the postamplifier may be pin selected to 3.5 db or 15.5 db to optimize gain range and output noise for 12-bit or 10-bit converter applications. the output may be limited to a user-selected clamping level, preventing input overload to a subsequent adc. an external resistor adjusts the clamping level. the operating temperature range is C40 c to +85 . the ad8331 is available in a 20-lead qsop package, and the ad8332 in 28-lead tssop and 32-lead lfcsp packages. they require a single 5 v supply, and the quiescent power consumption is 125 mw/ch. a power-down (enable) pin is provided.
ad8331/ad8332 rev. c | page 2 of 32 table of contents revision history.................................................................. 2 ad8331, ad8332specifications.................................................. 3 absolute maximum ratings............................................................ 6 esd caution ............................................................................ 6 ad8331, ad8332typical performance characteristics .......... 7 test circuits..................................................................................... 15 theory of operation ...................................................................... 17 overview...................................................................................... 17 low noise amplifier (lna)...................................................... 17 variable gain amplifier............................................................. 19 postamplifier ............................................................................... 21 applications..................................................................................... 22 lna C external components ................................................... 22 driving adcs ............................................................................. 24 overload ...................................................................................... 24 optional input overload protection. ...................................... 25 layout, grounding, and bypassing ......................................... 25 multiple input matching ........................................................... 25 disabling the lna...................................................................... 25 measurement considerations................................................... 26 ultrasound tgc application ................................................... 26 pin configuration and function descriptions........................... 30 ad8331........................................................................................ 30 ad8332........................................................................................ 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history revision c 11/03data sheet changed from rev. b to rev. c addition of new part...........................................................universal changes to figures ...............................................................universal updated outline dimensions..........................................................32 5/03data sheet changed from rev. a to rev. b edits to ordering guide....................................................................32 edits to ultrasound tgc application section................................25 added figure 71, figure 72, and figure 73......................................26 updated outline dimensions............................................................31 2/03data sheet changed from rev. 0 to rev. a edits to ordering guide.....................................................................32
ad8331/ad8332 rev. c | page 3 of 32 ad8331, ad8332specifications table 1. t a = 25c, v s = 5 v, r l = 500 ?, r s = r in = 50 ?, r fb = 280 ?, c sh = 22 pf, f = 10 mhz, r clmp = , c l = 1 pf, v cm pin floating, C4.5 db to +43.5 db gain (hilo = lo), and differential output voltage, unless otherwise specified. parameter conditions min typ max unit lna characteristics single-ended input to differential output 19 db gain input to output (sin gle-ended) 13 db input voltage range ac-coupled 275 mv r fb = 280 ? 50 ? r fb = 412 ? 75 ? r fb = 562 ? 100 ? r fb = 1.13 k? 200 ? input resistance r fb = 6 k? input capacitance 13 pf output impedance single-end ed, either output 5 ? C3 db small signal bandwidth v out = 0.2 v p-p 130 mhz slew rate 650 v/s input voltage noise r s = 0 ?, hi or lo gain, r fb = , f = 5 mhz 0.74 nv/hz input current noise r fb = , hi or lo gain, f = 5 mhz 2.5 pa/hz noise figure f = 10 mhz, lop output active termination match r s = r in = 50 ? 3.7 db unterminated r s = 50 ?, r fb = 2.5 db harmonic distortion @ lop1 or lop2 hd2 C56 dbc hd3 v out = 0.5 v p-p, single-ended, f = 10 mhz C70 dbc output short-circuit current pins lon, lop 165 ma lna + vga characteristics C3 db small signal bandwidth v out = 0.2 v p-p 120 mhz C3 db large signal bandwidth v out = 2 v p-p 110 mhz lo gain 300 v/s slew rate hi gain 1200 v/s input voltage noise r s = 0 ?, hi or lo gain, r fb = , f = 5 mhz 0.82 nv/hz noise figure v gain = 1.0 v r s = r in = 50 ?, f = 10 mhz, measured 4.15 db active termination match r s = r in = 200 ?, f = 5 mhz, simulated 2.0 db r s = 50 ?, r fb = , f = 10 mhz, measured 2.5 db unterminated r s = 200 ?, r fb = , f = 5 mhz, simulated 1.0 db v gain = 0.5 v, lo gain 48 nv/hz output-referred noise v gain = 0.5 v, hi gain 178 nv/hz output impedance, postamplif ier dc to 1 mhz 1 ? output signal range, postamplifier r l 500 ?, unclamped, either pin v cm 1.125 v differential 4.5 v p-p output offset voltage differential C50 5 +50 mv common-mode v gain = 0.5 v C125 C25 +100 mv output short-circuit current 45 ma
ad8331/ad8332 rev. c | page 4 of 32 parameter conditions min typ max unit harmonic distortion v gain = 0.5 v, v out = 1 v p-p hd2 C88 dbc hd3 f = 1 mhz C85 dbc hd2 C68 dbc hd3 f = 10 mhz C65 dbc input 1 db compression point v gain = 0.25 v, v out = 1 v p-p, f = 1 mhzC10 mhz 7 dbm 1 v gain = 0.72 v, v out = 1 v p-p, f = 1 mhz C80 dbc two-tone intermodulation distortion (imd3) v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz C72 dbc v gain = 0.5 v, v out = 1 v p-p, f = 1 mhz 38 dbm output third order intercept v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz 33 dbm channel-to-channel crosstalk (ad8332) v gain = 0.5 v, v out = 1 v p-p, f = 1 mhz C84 db overload recovery v gain = 1.0 v, v in = 50 mv p-p/1 v p-p, f = 10 mhz 5 ns group delay variation 5 mhz < f < 50 mhz, full gain range 2 ns accuracy 0.05 v < v gain < 0.10 v C1 +0.5 +2 db 0.10 v < v gain < 0.95 v C1 0.3 +1 db absolute gain error 2 0.95 v < v gain < 1.0 v C2 C1 +1 db gain law conformance 3 0.1 v < v gain < 0.95 v 0.2 db channel-to-channel gain matching 0.1 v < v gain < 0.95 v 0.1 db gain control interface (pin gain) gain scaling factor 0.10 v < v gain < 0.95 v 50 db/v lo gain C4.5 to +43.5 db gain range hi gain +7.5 to +55.5 db input voltage (v gain ) range 0 to 1.0 v input impedance 10 m? response time 48 db gain chan ge to 90% full scale 750 ns common-mode interface (pin vcmn) input resistance current limited to 1 ma 30 ? output cm offset voltage v cm = 2.5 v C125 C25 +100 mv voltage range v out = 2.0 v p-p 1.5 to 3.5 v enable interface (pins enb, enbl, enbv) logic level to enable power 2.25 5 v logic level to disable power 0 1.0 v pin enb 25 k? pin enbl 40 k? input resistance pin enbv 70 k? v inh = 30 mv p-p 300 s power-up response time v inh = 150 mv p-p 4 ms hilo gain range interface (pin hilo) logic level to select hi gain range 2.25 5 v logic level to select lo gain range 0 1.0 v input resistance 50 k? 1 all dbm values are referred to 50 ?, unless otherwise noted. 2 conformance to theoretical gain expression (see equation 1). 3 conformance to best fit db linear curve.
ad8331/ad8332 rev. c | page 5 of 32 parameter conditions min typ max unit output clamp interface (pin rclmp; hi or lo gain) accuracy hilo = lo r clmp = 2.74 k?, v out = 1 v p-p (clamped) 50 mv hilo = hi r clmp = 2.21 k?, v out = 1 v p-p (clamped) 75 mv mode interface (pin mode) logic level for positive gain slope 0 1.0 v logic level for negative gain slope 2.25 5 v input resistance 200 k? power supply (pins vps1, vps2, vpsv, vpsl, vpos) supply voltage 4.5 5.0 5.5 v quiescent current per channel 25 ma power dissipation per channel no signal 125 mw disable current ad8332 (vga and lna) 300 600 a ad8331 (vga and lna) 240 400 a ad8332 (enbl) each channel 12 ma ad8332 (enbv) each channel 13 ma ad8331 (enbl) 11 ma ad8331 (enbv) 14 ma psrr v gain = 0, f = 100 khz C68 db
ad8331/ad8332 rev. c | page 6 of 32 absolute maximum ratings table 2. absolute maximum ratings parameter rating voltage supply voltage (vpsn, vpsv, vpsl, vpos) 5.5 v input voltage (inhn) v s + 200 mv enb, enbl, enbv, hilo voltage v s + 200 mv gain voltage 2.5 v power dissipation ru-28 package (ad8332) 4 0.96 w cp-32 package (ad8332) 5 1.97 w rq-20 package (ad8331) 4 0.78 w temperature operating temperature C40c to +85c storage temperature C65c to +150c lead temperature (soldering 60 sec) 300c ja ru-28 package (ad8332) 4 68c/w cp-32 package (ad8332) 5 33c/w rq-20 package (ad8331) 4 83c/w jc ru-28 package (ad8332) 4 14c/w cp-32 package (ad8332) 5 33c/w rq-20 package (ad8331) 4 n/a 4 four-layer jedec board (2s2p). 5 exposed pad soldered to board, nine thermal vias in pad jedec 4-layer board j-std-51-9. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8331/ad8332 rev. c | page 7 of 32 ad8331, ad8332typical perform ance characteristics t a = 25c, v s = 5 v, r l = 500 ?, r s = r in = 50 ?, r fb = 280 ?, c sh = 22 pf, f = 10 mhz, r clmp = , c l = 1 pf, v cm = 2.5 v, C4.5 db to +43.5 db gain (hilo = lo), and differential signal voltage, unless otherwise specified. 0 0.2 v gain (v) 0.6 0.4 1.0 0.8 1.1 g a i n ( d b ) 40 50 30 10 0 20 ?10 60 mode = hi (ac package only) mode = lo hilo = lo 03199-c-003 hilo = hi figure 3. gain vs. v gain and mode (mode available on ac package) 03199-c-004 gain error (db) 0.5 1.0 2.0 1.5 00.2 v gain (v) 0.6 0.4 0 ?1.0 ?1.5 ?0.5 ?2.0 1.0 0.8 1.1 ?40 c +85 c +25 c figure 4. absolute gain error vs. v gain at three temperatures gain error (db) 0.5 1.0 2.0 1.5 0 0.2 v gain (v) 0.6 0.4 0 ?1.0 ?1.5 ?0.5 ?2.0 1.0 0.8 1.1 1mhz 30mhz 70mhz 03199-c-005 10mhz figure 5. absolute gain error vs. v gain at various frequencies 0 % o f u n i t s 10 20 30 40 50 ?0.1 gain error (db) 0.4 0 ?0.3 ?0.2 0.1 ?0.4 ?0.5 0.3 0.2 0.5 sample size = 80 units v gain = 0.5v 03199-c-006 figure 6. gain error histogram % of units 0.01 channel-to-channel gain match (db) 0 0.15 0.13 0.11 0.09 0.07 0.05 0.03 ?0.01 0.21 0.19 0.17 ?0.17 ?0.15 ?0.13 ?0.11 ?0.09 ?0.07 ?0.05 ?0.03 5 25 20 15 10 0 5 25 20 15 10 v gain = 0.7v sample size = 50 units v gain = 0.2v 03199-c-007 figure 7. gain match histogram for v gain = 0.2 v and 0.7 v g a i n ( d b ) ?10 0 10 20 40 30 50 100k ?20 frequency (hz) 1m 1g 100m 10m v gain = 1v 0.8v 0.6v 0.4v 0.2v 0v 03199-c-008 figure 8. frequency response for various values of v gain
ad8331/ad8332 rev. c | page 8 of 32 frequency (hz) gain (db) ?10 0 10 20 40 30 50 60 0.8v 0.6v 0.4v 0.2v 0v 1m 1g 100k 100m 10m 03199-c-009 v gain = 1v figure 9. frequency response for various values of v gain , hilo = hi gain (db) ?10 0 10 20 ?40 30 ?30 ?20 1m 1g 100k 100m 10m v gain =0.5v r in =r s =50 ? ,75 ? ,100 ? r in =r s =1k ? 03199-c-010 r in =r s = 500 ? r in =r s =200 ? frequency (hz) figure 10. frequency response for various matched source impedances frequency (hz) g a i n ( d b ) ?10 0 10 20 ?40 30 ?30 ?20 1m 1g 100k 100m 10m v gain = 0.5v r fb = 03199-c-011 figure 11. frequency response, unterminated, r s = 50 ? frequency (hz) c r o s s t a l k ( d b ) ?70 0 ?60 ?50 ?30 ?40 ?20 1m 100k 100m 10m ?10 ?90 ?80 0.7v 0.4v 0.9v v gain = 1v 0.5v v out = 1 v p-p 03199-c-012 figure 12. channel-to-channel crosstalk vs. frequency for various values of v gain frequency (hz) 1m 100k 100m 10m 0 50 45 40 35 30 25 20 15 10 5 03199-c-013 0.1 f coupling 1 f coupling group delay (ns) figure 13. group delay vs. frequency 1.1 0.4 0.2 0 0.3 0.1 0.9 0.7 0.5 0.8 0.6 1.0 ?20 ?10 0 10 20 ?20 ?10 0 10 20 t=+25 c lo gain t=+25 c 03199-c-014 v gain (v) offset voltage (mv) hi gain t=+85 c t=+85 c t = ?40 c t = ?40 c t = ?40 c t=+25 c t=+85 c t = ?40 c figure 14. representative different ial output offset voltage vs. v gain at three temperatures
ad8331/ad8332 rev. c | page 9 of 32 % total 50.5 gain scaling factor 0 50.4 49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 5 25 20 15 10 35 sample size = 100 0.2v < v gain < 0.7v 30 03199-b-015 figure 15. gain scaling factor histogram 100 100k 1m 10 1 0.1 10m 100m frequency (hz) o u t p u t i m p e d a n c e ( ? ) single ended, pin voh or vol r l = 03199-c-016 figure 16. output impedance vs. frequency frequency (hz) i n p u t i m p e d a n c e ( ? ) 100 1k 10 10k 1m 100k 100m 10m r fb = , c sh = 0pf r fb = 270 ? , c sh = 22pf r fb = 412 ? , c sh = 12pf r fb = 549 ? , c sh = 8.2pf r fb = 3.01k ? , c sh = 0pf r fb = 6.65k ? , c sh = 0pf r fb = 1.1k ? , c sh = 1.2pf 03199-c-017 figure 17. lna input impedance vs. frequency for various values of r fb and c sh 0 ? 17 ? 25j ?25j 50j ?50j 100j ?100j f = 100khz r in = 50 ? r fb = 270 ? r in = 75 ? , r fb = 412 ? r in = 100 ? , r fb = 549 ? , r in = 200 ? , r fb = 1.1k ? r in = 6k ? , r fb = 03199-b-018 figure 18. smith chart, s11 vs. frequency, 0.1 mhz to 200 mhz for various values of r fb 1g frequency (hz) 10m g a i n ( d b ) 100k ?10 ?5 0 5 20 10 15 100m 1m ?20 ?15 r in = 50 ? , 75 ? , and 100 ? r in = 200 ? r in = 200 ? r in = 500 ? r in = 1k ? 03199-c-019 figure 19. lna frequency response, single-ended, for various values of r in 1g frequency (hz) 10m g a i n ( d b ) 100k ?10 ?5 0 5 20 10 15 100m 1m ?20 ?15 r fb = 03199-c-020 figure 20. lna frequency response, unterminated, single-ended
ad8331/ad8332 rev. c | page 10 of 32 500 0 0.4 v gain (v) 1.0 0.6 300 0 100 400 200 0.2 0.8 o u t p u t - r e f e r r e d n o i s e ( n v / h z ) hilo = hi f = 10mhz hilo = lo 03199-c-021 figure 21. output-referred noise vs. v gain 1m 10m 0 100m 100k frequency (hz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 i n p u t n o i s e ( n v / h z ) r s = 0, r fb = , v gain = 1v hilo = lo or hi 03199-c-022 figure 22. short-circuit input-referred noise vs. frequency 1 0 0.4 v gain (v) 1.0 0.6 0.1 100 10 0.2 0.8 i n p u t n o i s e ( n v / h z ) r s = 0, r fb = , hilo = lo or hi, f = 10mhz 03199-c-023 figure 23. short-circuit input-referred noise vs. v gain 90 temperature ( c) 10 ?30 ?50 ?10 70 50 30 0.50 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 i n p u t n o i s e ( n v / h z ) r s = 0, r fb = , v gain = 1v, f = 10mhz 03199-c-024 figure 24. short-circuit input-referred noise vs. temperature 110 1.0 0.1 100 1k source resistance ( ? ) 10 i n p u t n o i s e ( n v / h z ) r s = thermal noise alone f = 5mhz, r fb = , v gain = 1v 03199-c-025 figure 25. input-referred noise vs. r s n o i s e f i g u r e ( d b ) 5 6 7 4 2 1 3 0 100 50 1k 75 ? 200 ? source resistance ( ? ) r in = 50 ? r fb = includes noise of vga simulation 100 ? 03199-c-026 figure 26. noise figure vs. r s for various values of r in
ad8331/ad8332 rev. c | page 11 of 32 n o i s e f i g u r e ( d b ) 40 50 0 0.2 v gain (v) 0.6 0.4 30 10 0 20 5 1.0 0.8 1.1 35 45 25 15 0.1 0.5 0.3 0.9 0.7 hilo = lo, r in = 50 ? hilo = lo, r fb = hilo = hi, r fb = hilo = hi, r in = 50 ? f = 10mhz, r s = 50 ? 03199-c-027 figure 27. noise figure vs. v gain n o i s e f i g u r e ( d b ) 30 10 20 gain (db) 35 25 20 0 5 55 45 60 25 15 10 15 30 50 40 hilo = hi, r in = 50 ? hilo = hi, r fb = hilo = lo, r in = 50 ? hilo = lo, r fb = f = 10mhz, r s = 50 ? 03199-c-028 figure 28. noise figure vs. gain harmonic distortion (dbc) ?70 ?60 ?50 ?40 ?100 ?90 ?80 100m 1m 10m hilo = hi, hd3 ?30 ?20 ?10 0 g = 30db v out =1v p-p frequency (hz) 03199-c-029 hilo = lo, hd3 hilo = hi, hd2 hilo = lo, hd2 figure 29. harmonic distortion vs. frequency h a r m o n i c d i s t o r t i o n ( d b c ) ?70 ?60 ?50 ?40 ?100 ?90 ?80 200 800 0 600 400 1.0k 2.0k 1.8k 1.6k 1.4k 1.2k ?30 r load ( ? ) hilo = lo, hd3 hilo = lo, hd2 f = 10mhz v out = 1v p-p hilo = hi, hd2 hilo = hi, hd3 03199-c-030 figure 30. harmonic distortion vs. r load h a r m o n i c d i s t o r t i o n ( d b c ) ?70 ?60 ?50 ?40 ?100 ?90 ?80 10 40 50 030 20 c load (pf) hilo = hi, hd3 hilo = lo, hd2 hilo = lo, hd3 f = 10mhz v out = 1v p-p 03199-c-031 hilo = hi, hd2 figure 31. harmonic distortion vs. c load h a r m o n i c d i s t o r t i o n ( d b c ) ?70 ?60 ?50 ?40 ?100 ?90 ?80 14 03 2 f = 10mhz gain = 30 db v out (v p-p) hilo = lo, hd3 hilo = hi, hd3 hilo = lo, hd2 03199-c-032 hilo = hi, hd2 figure 32. harmonic distortion vs. differential output voltage
ad8331/ad8332 rev. c | page 12 of 32 distortion (dbc) 0 ?100 ?80 ?60 ?40 ?20 0 ?120 v out = 1v p-p 03199-c-033 v gain (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 hilo = lo, hd2 hilo = hi, hd2 hilo = lo, hd3 hilo = hi, hd3 input range limited when hilo = lo figure 33. harmonic distortion vs. v gain , f = 1 mhz ?100 ?80 ?60 ?40 ?20 0 ?120 input rang e limited when hilo = lo hilo = hi, hd2 hilo = hi, hd3 hilo = lo, hd2 hilo = lo, hd3 0 v gain (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v out = 1v p-p 03199-c-034 distortion (dbc) figure 34. harmonic distortion vs. v gain , f = 10 mhz 0.4 0.2 i n p u t p o w e r ( d b m ) 0 0.3 0.1 ?30 0.9 0.7 0.5 0.8 0.6 1.0 5 0 ?5 ?10 ?15 ?20 ?25 10 v gain (v) f = 10mhz hilo = hi hilo = lo 03199-c-035 figure 35. input 1 db compression vs. v gain 100m frequency (hz) 1m i m d 3 ( d b c ) 10m ?10 ?90 ?80 ?70 ?60 ?30 ?50 ?40 ?20 0 v out = 1v p-p composite (f 1 + f 2 ) g = 30db 03199-c-036 figure 36. imd3 vs. frequency o u t p u t i p 3 ( d b m ) v gain (v) 15 20 25 30 0 5 10 0.1 0.4 0 0.3 0.2 1.0 0.9 0.8 0.7 0.6 0.5 40 35 hilo = hi, 1mhz hilo = hi, 10mhz hilo = lo, 10mhz hilo = lo, 1mhz v out = 1v p-p composite (f 1 + f 2 ) 03199-c-037 figure 37. output third order intercept vs. v gain 100 90 10 0 2mv 50mv 10ns 03199-c-038 figure 38. small signal pulse response, g = 30 db, top: input, bottom: output voltage, hilo = hi or lo
ad8331/ad8332 rev. c | page 13 of 32 100 90 10 0 500mv 10ns 03199-c-039 20mv figure 39. large signal pulse response, g = 30 db, hilo = hi or lo, top: input, bottom: output voltage 10 ?10 ?30 0 ?20 ?2 60 40 20 50 30 ?40 1 0 ?1 2 80 70 input 03199-c-040 v out (v) time (ns) g = 30db c l = 50pf c l = 0pf input is not to scale figure 40. large signal pulse response for various capacitive loads, c l = 0 pf, 10 pf, 20 pf, 50 pf 400ns 200mv 500mv 03199-b-041 figure 41. pin gain transient response, top: v gain , bottom: output voltage v o u t ( v p - p ) 010 30 20 50 40 1 4 3 2 0 5 r clmp (k ? ) hilo = lo hilo = hi 03199-c-042 figure 42. clamp level vs. r clmp 30 time (ns) 10 v o u t ( v ) ?10 20 0 ?4 60 40 50 1 0 ?1 2 4 3 ?2 ?3 g = 40db r clmp = 48.1k ? r clmp = 16.5k ? r clmp = 7.15k ? r clmp = 2.67k ? 03199-c-043 figure 43. clamp level pulse response 100 90 10 0 100ns 200mv 03199-b-044 figure 44. lna overdrive recovery, v inh 0.05 v p-p to 1 v p-p burst, v gain = 0.27 v, vga output shown
ad8331/ad8332 rev. c | page 14 of 32 100 90 10 0 100ns 50mv 03199-b-045 figure 45. vga overdrive recovery, v inh 4 mv p-p to 70 mv p-p burst, v gain = 1 v, vga output shown attenuated 24 db 100 90 10 0 100ns 50mv 03199-b-046 figure 46. vga overdrive recovery, v inh 4 mv p-p to 275 mv p-p burst, v gain = 1 v, vga output shown attenuated 24 db 1ms 200mv 2v 03199-b-047 figure 47. enable response, top: v enb , bottom: v out , v inh = 30 mv p-p 1v 2v 1ms 03199-b-048 figure 48. enable response, large signal, top: v enb , bottom: v out , v inh = 150 mv p-p frequency (hz) p s r r ( d b ) 1m 100k 100m 10m ?80 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 vps1, v gain = 0.5v vps1, v gain = 0v vpsv, v gain = 0.5v 03199-c-049 figure 49. psrr vs. frequency (no bypass capacitor) 40 0 ?40 40 45 50 55 60 20 ?20 30 100 80 60 20 25 35 03199-c-050 temperature ( c) ad8331 ad8332 v gain = 0.5v quiescent supply current (ma) figure 50. quiescent supply current vs. temperature
ad8331/ad8332 rev. c | page 15 of 32 test circuits lmd 1.8nf 22pf fb* 120nh in out 0.1 f dut 03199-c-051 *ferrite bead network analyzer 0.1 f 28 ? 237 ? 28 ? 1:1 50 ? 50 ? 0.1 f 270 ? inh 237 ? 0.1 f figure 51. gain and bandwidth measurements 1:1 in lmd dut 0.1 f 22pf fb* 120nh 0.1 f 03199-c-052 *ferrite bead 50 ? 0.1 f inh 0.1 f 28 ? 237 ? 237 ? 28 ? 50 ? 1.8nf 270 ? oscilloscope figure 52. transient measurements 1:1 lmd inh dut 0.1 f spectrum analyzer in 22pf 1 ? 49 ? 50 ? ab g *ferrite bead fb* 120nh 0.1 f 0.1 f 50 ? 03199-c-053 0.1 f figure 53. used for noise measurements
ad8331/ad8332 rev. c | page 16 of 32 in 50 ? 0.1 f 28 ? 03199-c-054 28 ? 0.1 f 0.1 f 0.1 f 50 ? spectrum analyzer 120nh fb* 22pf lmd inh dut 1:1 1.8nf 270 ? 237 ? 237 ? *ferrite bead figure 54. distortion 270 ? 1:1 network analyzer lmd inh dut 1.8nf 0.1 f 22pf fb* 120nh 50 ? in out *ferrite bead 28 ? 237 ? 50 ? 50 ? 0.1 f 0.1 f 0.1 f 237 ? 28 ? 50 ? 03199-c-055 figure 55. s11 measurements
ad8331/ad8332 rev. c | page 17 of 32 theory of operation overview the following discussion applies to all part numbers. figure 56 and figure 1 are functional block diagrams of the ad8331 and ad8332, respectively. lna 2 1 6 3 lmd inh coml vpsl 10 gain comm lna bias (v mid ) vga ? g = ?48db to 0db +21db bias and interpolator 20 4 5 7 8 17 19 18 v mid post amp1 12 clamp gain int 11 19 15 16 9 3.5db/ 15.5db enbl enbv rclmp voh vol mode lon lop vip vin vpos vcm 14 hilo comm ad8331 03199-c-056 figure 56. functional block diagram ad8331 each channel contains an lna that provides user-adjustable input impedance termination, a differential x-amp vga, and a programmable gain postamplifier with adjustable output voltage limiting. figure 57 shows a simplified block diagram. vol voh lna clamp* ? + inh lmd lop lon hilo vcm preamplifier 19db x-amp vga postamp [(?48 to 0) + 21] db 3.5db/15.5db gain interface* gain b i a s a n d i n t e r p o l a t o r * vin vip *shared between channels rclmp bias (v mid ) v mid 03199-b-057 figure 57. simplified block diagram the linear-in-db gain control interface is trimmed for slope and absolute accuracy. the overall gain range is 48 db, extending from C4.5 db to +43.5 db or from +7.5 db to +55.5 db, depending on the setting of the hilo pin. the slope of the gain control interface is 50 db/v, and the gain control range is 40 mv to 1 v, leading to the following expressions for gain: ( ) () ( ) 1 , 5 6 50 ) ( lo hilo db . C v v db db gain gain = = or ( ) () ( ) 2 , 5 5 50 ) ( hi hilo db . v v db db gain gain = + = the gain characteristics are shown in figure 58. gain (db) 40 50 00.2 v gain (v) 0.6 0.4 30 10 0 20 ?10 1.0 0.8 1.1 60 hilo = hi hilo = lo mode = lo mode = hi (where available) 03199-c-058 figure 58. gain control characteristics when mode is set high, (where available): ( ) () () 3 = , 5 45 + 50 C = ) ( lo hilo db . v v db db gain gain or ( ) () () 4 = , 5 57 + 50 C = ) ( hi hilo db . v v db db gain gain the lna converts a single-ended input to a differential output with a voltage gain of 19 db. when only one output is used, the gain is 13 db. the inverting output is used for active input impedance termination. each of the lna outputs is capacitively coupled to a vga input. the vga consists of an attenuator with a range of 48 db followed by an amplifier with 21 db of gain, for a net gain range of C27 db to +21 db. the x-amp gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. the final stage is a logic programmable amplifier with gains of 3.5 db or 15.5 db. the lo and hi gain modes are optimized for 12-bit and 10-bit a/d converter applications, in terms of output-referred noise and absolute gain range. output voltage limiting may be programmed by the user. low noise amplifier (lna) good noise performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following vga. active impedance control optimizes noise performance for applications that benefit from input matching.
ad8331/ad8332 rev. c | page 18 of 32 a simplified schematic of the lna is shown in figure 59. inh is capacitively coupled to the source. an on-chip bias generator centers the output dc levels at 2.5 v and the input voltages at 3.25 v. a capacitor c lmd of the same value as the input coupling capacitor c inh is connected from the lmd pin to ground. vpos inh lop lmd lon r s c inh q1 q2 i 0 c lmd c sh r fb c fb 03199-c-059 i 0 i 0 i 0 figure 59. simplified lna schematic the lna supports differential output voltages as high as 5 v p-p with positive and negative excursions of 1.25 v, about a common-mode voltage of 2.5 v. since the differential gain magnitude is 9, the maximum input signal before saturation is 275 mv or 550 mv p-p. overload protection ensures quick recovery time from large input voltages. since the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the esd protection. low value feedback resistors and the current-driving capability of the output stage allow the lna to achieve a low input- referred voltage noise of 0.74 nv/hz. this is achieved with a modest current consumption of 10 ma per channel (50 mw). on-chip resistor matching results in precise gains of 4.5 per side (9 differential), critical for accurate impedance control. the use of a fully differential topology and negative feedback minimizes distortion. low hd2 is particularly important in second harmonic ultrasound imaging applications. differential signaling enables smaller swings at each output, further reducing third order distortion. active impedance matching the lna supports active impedance matching through an external shunt feedback resistor from pin lon to pin inh. the input resistance r in is given by equation 5, where a is the single-ended gain of 4.5, and 6 k? is the unterminated input impedance. () 5 + 33 6 = 6 + 1 = fb fb fb in r k r k k a r r c fb is needed in series with r fb , since the dc levels at pins lon and inh are unequal. expressions for choosing r fb in terms of r in and for choosing c fb are found in the applications section. c sh and the ferrite bead enhance stability at higher frequencies where the loop gain declines and prevents peaking. frequency response plots of the lna are shown in figure 19 and figure 20. the bandwidth is approximately 130 mhz for matched input impedances of 50 ? to 200 ? and declines at higher source impedances. the unterminated bandwidth (r fb = ) is approximately 80 mhz. each output can drive external loads as low as 100 ? in addition to the 100 ? input impedance of the vga (200 ? differential). capacitive loading up to 10 pf is permissible. all loads should be ac-coupled. typically, pin lop output is used as a single- ended driver for auxiliary circuits, such as those used for doppler mode ultrasound imaging, and pin lon drives r fb . alternatively, a differential external circuit can be driven from the two outputs, in addition to the active feedback termination. in both cases, important stability considerations discussed in the applications section should be carefully observed. the impedance at each lna output is 5 ?. a 0.4 db reduction in open-circuit gain results when driving the vga, and 0.8 db with an additional 100 ? load at the output. the differential gain of the lna is 6 db higher. if the load is less than 200 ? on either side, a compensating load is recommended on the opposite output. lna noise the input-referred voltage noise sets an important limit on system performance. the short-circuit input voltage noise of the lna is 0.74 nv/hz or 0.82 nv/hz (at maximum gain), including the vga noise. the open-circuit current noise is 2.5 pa/hz. these measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in figure 60. figure 61 and figure 62 are simulations extracted from these results, and the 4.1 db nf measurement with the input actively matched to a 50 ? source. unterminated (r fb = ) operation exhibits the lowest equivalent input noise and noise figure. figure 61 shows the noise figure versus source resistance, rising at low r s , where the lna voltage noise is large compared to the source noise, and again at high r s due to current noise. the vgas input-referred voltage noise of 2.7 nv/hz is included in all of the curves.
ad8331/ad8332 rev. c | page 19 of 32 v out unterminated + ? v in r in r s v out resistive termination + ? v in r in r s r s v out active impedance match ?r s = r in + ? v in r in r fb r fb 1 + 4.5 r s r in = 03199-c-060 figure 60. input configurations n o i s e f i g u r e ( d b ) 5 6 7 4 2 1 3 0 100 50 1k r s ( ? ) active impedance match resistive termination (r s = r in ) unterminated simulation includes noise of vga 03199-c-061 figure 61. noise figure vs. r s for resistive, active matched, and unterminated inputs noise f igure (db) 5 6 7 4 2 1 3 0 100 50 1k r in = 50 ? 70 ? r fb = r s ( ? ) 200 ? includes noise of vga 100 ? simulation 03199-c-081 figure 62. noise figure vs. r s for various fixed values of r in , actively matched the primary purpose of input impedance matching is to improve the system transient response. with resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the lnas input voltage noise generator. with active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + lna gain ). figure 61 shows their relative noise figure (nf) performance. in this graph, the input impedance has been swept with r s to preserve the match at each point. the noise figures for a source impedance of 50 are 7.1 db, 4.1 db, and 2.5 db, respectively, for the resistive, active, and unterminated configurations. the noise figures for 200 are 4.6 db, 2.0 db, and 1.0 db, respectively. figure 62 is a plot of the nf versus r s for various values of r in , which is helpful for design purposes. the plateau in the nf for actively matched inputs mitigates source impedance variations. for comparison purposes, a preamp with a gain of 19 db and noise spectral density of a 1.0 nv/hz, combined with a vga with 3.75 nv/hz, would yield a noise figure degradation of approximately 1.5 db (for most input impedances), significantly worse than the ad8332 performance. the equivalent input noise of the lna is the same for single- ended and differential output applications. the lna noise figure improves to 3.5 db at 50 without vga noise, but this is exclusive of noise contributions from other external circuits connected to lop. a series output resistor is usually recommended for stability purposes, when driving external circuits on a separate board (see the applications section). in low noise applications, a ferrite bead is even more desirable. variable gain amplifier the differential x-amp vga provides precise input attenuation and interpolation. it has a low input-referred noise of 2.7 nv/hz and excellent gain linearity. a simplified block diagram is shown in figure 63. gain interpolator (both channels) post-amp vip gain r 6db 2r 48db vin g m 03199-c-063 post-amp figure 63. simplified vga schematic
ad8331/ad8332 rev. c | page 20 of 32 x-amp vga the input of the vga is a differential r-2r ladder attenuator network, with 6 db steps per stage and a net input impedance of 200 ? differential. the ladder is driven by a fully differential input signal from the lna and is not intended for single-ended operation. lna outputs are ac-coupled to reduce offset and isolate their common-mode voltage. the vga inputs are biased through the ladders center tap connection to vcm, which is typically set to 2.5 v and is bypassed externally to provide a clean ac ground. the signal level at successive stages in the input attenuator falls from 0 db to C48 db, in 6 db steps. the input stages of the x-amp are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. with overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 db to C48 db. this circuit technique results in excellent, linear-in-db gain law conformance and low distortion levels and deviates 0.2 db or less from ideal. the gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. the x-amp inputs are part of a gain-of-12 feedback amplifier, which completes the vga. its bandwidth is 150 mhz. the input stage is designed to reduce feedthrough to the output and ensure excellent frequency response uniformity across gain setting (see figure 8 and figure 9). gain control position along the vga attenuator is controlled by a single- ended analog control voltage, v gain , with an input range of 40 mv to 1.0 v. the gain control scaling is trimmed to a slope of 50 db/v (20 mv/db). values of v gain beyond the control range saturate to minimum or maximum gain values. both channels of the ad8332 are controlled from a single gain interface to preserve matching. gain can be calculated using equations 1 and 2. gain accuracy is very good since both the scaling factor and absolute gain are factory trimmed. the overall accuracy relative to the theoretical gain expression is 1 db for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. the gain error relative to a best-fit line for a given set of conditions is typically 0.2 db. gain matching between channels is better than 0.1 db (see figure 7, which shows gain errors in the center of the control range). when v gain < 0.1 or > 0.95, gain errors are slightly greater. the gain slope may be inverted, as shown in figure 58 (avail- able in most versions). the gain drops with a slope of C50 db/v across the gain control range from maximum to minimum gain. this slope is useful in applications, such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. the inverse gain mode is selected by setting the mode pin hi. gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to max- imum gain. vga noise in a typical application, a vga compresses a wide dynamic range input signal to within the input span of an adc. while the input-referred noise of the lna limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the vga, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. this limit is set in accordance with the quantization noise floor of the adc. output and input-referred noise as a function of v gain are plotted in figure 21 and figure 23 for the short-circuited input condition. the input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. the output-referred noise is flat over most of the gain range, since it is dominated by the fixed output-referred noise of the vga. values are 48 nv/hz in lo gain mode and 178 nv/hz in hi gain mode. at the high end of the gain control range, the noise of the lna and source prevail. the input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the vga becomes very small. at lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. the instantaneous dynamic range of the system is not lost, however, since the input capacity increases with it. the contribution of the adc noise floor has the same dependence as well. the important relationship is the magnitude of the vga output noise floor relative to that of the adc. with its low output-referred noise levels, these devices ideally drive low-voltage adcs. the converter noise floor drops 12 db for every 2 bits of resolution and drops at lower input full-scale voltages and higher sampling rates. adc quantization noise is discussed in the applications section. the preceding noise performance discussion applies to a differential vga output signal. although the lna noise performance is the same in single-ended and differential applications, the vga performance is not. the noise of the vga is significantly higher in single-ended usage, since the contribution of its bias noise is designed to cancel in the differential signal. a transformer can be used with single-ended applications when low noise is desired.
ad8331/ad8332 rev. c | page 21 of 32 gain control noise is a concern in very low noise applications. thermal noise in the gain control interface can modulate the channel gain. the resultant noise is proportional to the output signal level and usually only evident when a large signal is present. its effect is observable only in lo gain mode, where the noise floor is substantially lower. the gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 mhz. care should be taken to minimize noise impinging at the gain input. an external rc filter may be used to remove v gain source noise. the filter bandwidth should be sufficient to accommodate the desired control bandwidth. common-mode biasing an internal bias network connected to a midsupply voltage establishes common-mode voltages in the vga and postamp. an externally bypassed buffer maintains the voltage. the bypass capacitors form an important ac ground connection, since the vcm network makes a number of important connections internally, including the center tap of the vgas differential input attenuator, the feedback network of the vgas fixed gain amplifier, and the feedback network of the postamplifier in both gain settings. for best results, use a 1 nf and a 0.1 f capacitor in parallel, with the 1 nf nearest to pin vcm. separate vcm pins are provided for each channel. for dc-coupling to a 3 v adc, the output common-mode voltage is adjusted to 1.5 v by biasing the vcm pin. postamplifier the final stage has a selectable gain of 3.5 db or 15.5 db, set by the logic pin hilo. these correspond to linear gains of 1.5 or 6. a simplified block diagram of the postamplifier is shown in figure 64. separate feedback attenuators implement the two gain settings. these are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 db bandwidth between the two gain modes (~150 mhz). the slew rate is 1200 v/s in hi gain mode and 300 v/s in lo gain mode. the feedback networks for hi and lo gain modes are factory trimmed to adjust the absolute gains of each channel. noise the topology of the postamplifier provides constant input- referred noise with the two gain settings and variable output- referred noise. the output-referred noise in hi gain mode increases (with gain) by four. this setting is recommended when driving converters with higher noise floors. the extra gain boosts the output signal levels and noise floor appropriately. when driving circuits with lower input noise floors, the lo gain mode optimizes the output dynamic range. gm2 + ? gm1 voh vol vcm gm1 gm2 f1 f2 03199-b-064 figure 64. postamplifier block diagram although the quantization noise floor of an adc depends on a number of factors, the 48 nv/hz and 178 nv/hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. an additional technique, described in the applications section, can extend the noise floor even lower for possible use with 14-bit adcs. output clamping outputs are internally limited to a level of 4.5 v p-p differential when operating at a 2.5 v common-mode voltage. the postamp implements an optional output clamp engaged through a resistor from r clmp to ground. table shows a list of recommended resistor values. output clamping can be used for adc input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 v. the user should be aware that distortion products increase as output levels approach the clamping levels and should adjust the clamp resistor accordingly. also, see the applications section. the accuracy of the clamping levels is approximately 5% in lo or hi mode. figure 65 illustrates the output characteristics for a few values of r clmp . ?3 ?2 v inh (v) v oh , v ol (v) 0 ?1 0.5 2 13 1.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 5.0 8.8k ? 3.5k ? r clmp = r clmp = 1.86k ? 03199-c-065 figure 65. output clamping characteristics
ad8331/ad8332 rev. c | page 22 of 32 applications lna C external components the lmd pin (connected to the bias circuitry) must be bypassed to ground, and signal source to the inh pin capacitively coupled using 2.2 nf to 0.1 f capacitors (see figure 66). the unterminated input impedance of the lna is 6 k. the user may synthesize any lna input resistance between 50 and 6 k. r fb is calculated according to equation 6 or selected from table . () () () 6 C 6 33 = in in fb r k r k r table 3. lna external component values for common source impedances r in (?) r fb (nearest std 1% value, ?) c sh (pf) 50 280 22 75 412 12 100 562 8 200 1.13k 1.2 500 3.01k none 6k none when active input termination is used, a 0.1 f capacitor (c fb ) is required to isolate the input and output bias voltages of the lna. the shunt input capacitor, c sh , reduces gain peaking at higher frequencies where the active termination match is lost due to the hf gain roll-off of the lna. suggested values are shown in table ; for unterminated applications, reduce the capacitor value by half. when a long trace to pin inh is unavoidable, or if both lna outputs drive external circuits, a small ferrite bead (fb) in series with pin inh preserves circuit stability with negligible effect on noise. the bead shown is 75 ? at 100 mhz (murata blm21 or equivalent). other values may prove useful. figure 67 shows the interconnection details of the lna output. capacitive coupling between lna outputs and the vga inputs is required because of differences in their dc levels and to eliminate the offset of the lna. capacitor values of 0.1 f are recommended. there is 0.4 db loss in gain between the lna output and the vga input due to the 5 output resistance. additional loading at the lop and lon outputs will affect lna gain. 21 22 23 24 28 25 26 27 15 16 20 17 18 19 8 7 6 5 1 4 3 2 14 13 9 12 11 10 vcm2 rclmp comm vol2 voh2 vip2 gain vin2 lop2 com2 lmd2 lon2 vps2 inh2 com1 lop1 lmd1 lon1 vps1 inh1 voh1 enb vip1 vcm1 vin1 vpsv vol1 hilo 0.1 f c fb * c lmd 0.1 f 1nf 5v 5v 1n f r fb * 5v +5v c sh * * * lna source vga out vga out 5v 1nf 0.1 f * see text lna out 1nf v gain fb 1nf 0.1 f 0.1 f 0.1 f 0.1 f 1nf 0.1 f 03199-c-066 figure 66. basic connections for a typical channel (ad8332 shown) 50 ? lna vin vip lop vcm 100 ? 5 ? lon to ext circuit to ext circuit c sh 5 ? 50 ? 100 ? 03199-c-067 figure 67. interconnections of the lna and vga both lna outputs are available for driving external circuits. pin lop should be used in those instances when a single-ended lna output is required. the user should be aware of stray capacitance loading of the lna outputs, in particular lon. the lna can drive 100 in parallel with 10 pf. if an lna output is routed to a remote pc board, it will tolerate a load capacitance up to 100 pf with the addition of a 49.9 series resistor or ferrite 75 /100 mhz bead.
ad8331/ad8332 rev. c | page 23 of 32 gain input pin gain is common to both channels of the ad8332. the input impedance is nominally 10 m ? and a bypass capacitor from 100 pf to1 nf is recommended. parallel connected devices may be driven by a common voltage source or dac. decoupling should take into account any bandwidth considerations of the drive waveform, using the total distributed capacitance. if gain control noise in lo gain mode becomes a factor, maintaining 15 nv/hz noise at the gain pin will ensure satisfactory noise performance. internal noise prevails below 15 nv/hz at the gain pin. gain control noise is negligible in hi gain mode. vcm input the common-mode voltage of pins vcm, vol, and voh defaults to 2.5 vdc. with output ac-coupled applications, the vcm pin will be unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. the vga outputs may be dc connected to a differential load, such as an adc. common-mode output voltage levels between 1.5 v and 3.5 v may be realized at pins voh and vol by applying the desired voltage at pin vcm. dc-coupled operation is not recommended when driving loads on a separate pc board. the voltage on the vcm pin is sourced by an internal buffer with an output impedance of 30 and a 2 ma default output current (see figure 68). if the vcm pin is driven from an external source, its output impedance should be <<30 and its current drive capability should be >>2 ma. if the vcm pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. when a common-mode voltage other than 2.5 v is used, a voltage-limiting resistor, r clmp , is needed to protect against overload. v cm new v cm r o << 30 ? 100pf 2ma max 30 ? 0.1 f internal circuitry ac grounding for internal circuitry 03199-b-068 figure 68. vcm interface logic inputsenb, mode, and hilo the input impedance of all enable pins is nominally 25 k and may be pulled up to 5 v (a pull-up resistor is recommended) or driven by any 3 v or 5 v logic families. the enable pins perform a power-down function, when disabled, the vga outputs are near ground. multiple devices may be driven from a common source. consult the pin-function tables for circuit functions controlled by the enable pins. pin hilo is compatible with 3 v or 5 v cmos logic families. it is either connected to ground or pulled up to 5 v, depending on the desired gain range and output noise. optional output voltage limiting the rclmp pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. the peak-to-peak limited voltage is adjusted by a resistor to ground, and table lists several voltage levels and the corresponding resistor value. unconnected, the default limiting level is 4.5 v p-p. note that third harmonic distortion will increase as waveform amplitudes approach clipping. for lowest distortion, the clamp level should be set higher than the converter input span. a clamp level of 1.5 v p-p is recommended for a 1 v p-p linear output range, 2.7 v p-p for a 2 v p-p range, or 1 v p-p for a 0.5 v p-p operation. the best solution will be determined experimentally. figure 69 shows third harmonic distortion as a function of the limiting level for a 2 v p-p output signal. a wider limiting level is desirable in hi gain mode. h d 3 ( d b c ) 5.0 ?50 ?40 ?30 ?80 ?70 ?60 2.0 3.5 1.5 3.0 2.5 4.0 4.5 ?20 clamp limit level (v p-p) v gain = 0.75v hilo = hi hilo = lo 03199-c-069 figure 69. hd3 vs. clamping level for 2 v p-p differential input
ad8331/ad8332 rev. c | page 24 of 32 table 4. clamp resistor values clamp resistor value (k?) clamp level (v p-p) hilo = lo hilo = hi 0.5 1.21 1.0 2.74 2.21 1.5 4.75 4.02 2.0 7.5 6.49 2.5 11 9.53 3.0 16.9 14.7 3.5 26.7 23.2 4.0 49.9 39.2 4.4 100 73.2 output filtering and series resistor requirements to ensure stability at the high end of the gain control range, series resistors or ferrite beads are recommended for the outputs when driving large capacitive loads, or circuits on other boards,. these components can be part of the external noise filter. recommended resistor values are 84.5 ? for lo gain mode and 100 ? for hi gain mode (see figure 66) and are placed near pins voh and vol. lower value resistors are permissible for applications with nearby loads or with gains less than 40 db. lower values are best selected empirically. an antialiasing noise filter is typically used with an adc. filter requirements are application dependent. when the adc resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and mitigates charge kickback from the adc inputs. any series resistance beyond that required for output stability should be placed on the adc board. figure 70 shows a second order low-pass filter with a bandwidth of 20 mhz. the capacitor is chosen in conjunction with the 10 pf input capacitance of the adc. 18pf optional backplane 84.5 ? 0 . 1 f 0 . 1 f 1 . 5 h 1 . 5 h 158 ? 158 ? 84.5 ? adc figure 70. 20 mhz second-order low-pass filter driving adcs the output drive will accommodate a wide range of adcs. the noise floor requirements of the vga will depend on a number of application factors, including bit resolution, sampling rate, full-scale voltage, and the bandwidth of the noise/antialias filter. the output noise floor and gain range can be adjusted by selecting hi or lo gain mode. the relative noise and distortion performance of the two gain modes can be compared in figure 21 and figure 27 through figure 37. the 48 nv/hz noise floor of the lo gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). both gain modes can accommodate adc full- scale voltages as high as 4 v p-p. since distortion performance remains favorable for output voltages as high as 4 v p-p (see figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. the circuit in figure 71 has an output full-scale range of 2 v p-p, a gain range of C10.5 db to +37.5 db, and an output noise floor of 24 nv/hz, making it suitable for some 14-bit adc applications. voh vol lpf 4v p-p diff, 48n v/ 187 ? 2v p-p diff, 24n v/ 2:1 374 ? hz 187 ? adc ad6644 hz 03199-c-071 figure 71. adjusting the noise floor for 14-bit adcs overload these devices respond gracefully to large signals that overload its input stage and to normal signals that overload the vga when the gain is set unexpectedly high. each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. signals larger than 275 mv at the lna input are clipped to 5 v p-p differential prior to the input of the vga. figure 44 shows the response to a 1 v p-p input burst. the symmetric overload waveform is important for applications, such as cw doppler ultrasound, where the spectrum of the lna outputs during overload is critical. the input stage is also designed to accommodate signals as high as 2.5 v without triggering the slow-settling esd input protection diodes. both stages of the vga are susceptible to overload. postamp limiting is more common and results in the clean-limited output characteristics found in figure 45. under more extreme conditions, the x-amp will overload, causing the minor glitches evident in figure 46. recovery is fast in all cases. the graph in figure 72 summarizes the combinations of input signal and gain that lead to the different types of overload.
ad8331/ad8332 rev. c | page 25 of 32 g a in ( d b ) 1m lo gain mode 15mv ?4.5 25mv l n a o v e r l o a d x-amp overload postamp overload x-amp overload postamp overload 29db 43.5 input amplitude (v) .275 0.1 10m 24.5db g a in ( d b ) hi gain mode 4mv 7.5 25mv l n a o v e r l o a d 41db 56.5 input amplitude (v) 24.5db 1 1m 0.275 0.1 10m 1 03199-c-072 figure 72. overload gain and signal conditions the previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response. when no r clmp resistor is provided, this level defaults to near 4.5 v p-p differential to protect outputs centered at a 2.5 v common mode. when other common-mode levels are set through the vcm pin, the value of r clmp should be chosen for graceful overload. a value of 8.3 k? or less is recommended for 1.5 v or 3.5 v common-mode levels (7.2 k? for hi gain mode). this limits the output swing to just above 2 v p-p diff. optional input overload protection. applications in which high transients are applied to the lna input may benefit from the use of clamp diodes. a pair of back- to-back schottky diodes can reduce these transients to manageable levels. figure 73 illustrates how such a diode- protection scheme may be connected. 20 19 4 3 2 lon vps inh comm enbl 0.1 f c sh fb c fb bas40-04 r sh r fb 2 3 1 optional schottky overload clamp 03199-c-072 figure 73. input overload clamping when selecting overload protection, the important parameters are forward and reverse voltages and t rr (or rr .). the infineon bas40 series shown in figure 73 has a rr of 100 ps and v f of 310 mv at 1 ma. many variations of these specifications can be found in vendor catalogs. layout, grounding, and bypassing due to their excellent high frequency characteristics, these devices are sensitive to their pcb environment. realizing expected performance requires attention to detail critical to good high speed board design. a multilayer board with power and ground plane is recommended, and unused area in the signal layers should be filled with ground. the multiple power and ground pins provide robust power distribution to the device and must all be connected. the power supply pins should each be with multiple values of high frequency ceramic chip capacitors to maintain low impedance paths to ground over a wide frequency range. these should have capacitance values of 0.01 f to 0.1 f in parallel with 100 pf to 1 nf, and be placed as close as possible to the pins. the lna power pins should be decoupled from the vga using ferrite beads. together with the decoupling capacitors, ferrite beads help eliminate undesired high frequencies without reducing the headroom, as do small value resistors. several critical lna areas require special care. the lon and lop output traces must be as short as possible before connecting to the coupling capacitors connected to pins vin and vip. r fb must be placed nearby the lon pin as well. resistors must be placed as close as possible to the vga output pins vol and voh to mitigate loading effects of connecting traces. values are discussed in the section entitled output filtering and series resistor requirements. signal traces must be short and direct to avoid parasitic effects. wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. pcb traces should be kept adjacent when running differential signals over a long distance. multiple input matching matching of multiple sources with dissimilar impedances can be accomplished as shown in the circuit of figure 75. a relay and low supply voltage analog switch may be used to select between multiple sources and their associated feedback resistors. an adg736 dual spdt switch is shown in this example; however, multiple switches are also available and users are referred to the analog devices selection guide for switches and multiplexers. disabling the lna where accessible, connection of the lna enable pin to ground will power down the lna, resulting in a current reduction of about half. in this mode, the lna input and output pins may be left unconnected, however the power must be connected to all the supply pins for the disabling circuit to function. figure 74 illustrates the connections using an ad8331 as an example.
ad8331/ad8332 rev. c | page 26 of 32 15 16 20 17 18 19 8 7 6 5 1 4 3 2 9 13 10 comm vip lop coml lmd lon vps inh comm enbv enbl gain 0.1 f hilo +5v +5v c fb 0.018 f nc voh vol vout vpos +5v 14 11 12 vcm r clmp nc nc nc vin 0.1 f ad8331 mode 03199-c-074 gain mode vcm clmp hilo vin figure 74. disabling the lna inh lna 5 ? lmd lop adg736 lon 200 ? 50 ? 0.1 f 18nf selectr fb 280 ? 1.13k ? ad8332 03199-c-075 5 ? figure 75. accommodating multiple sources measurement considerations figure 51 through figure 55 show typical measurement configurations and proper interface values for measurements with 50 ? conditions. short-circuit input noise measurements are made using figure 53. the input-referred noise level is determined by dividing the output noise by the numerical gain between point a and point b and accounting for the noise floor of the spectrum analyzer. the gain should be measured at each frequency of interest and with low signal levels since a 50 ? load is driven directly. the generator is removed when noise measurements are made. ultrasound tgc application the ad8332 ideally meets the requirements of medical and industrial ultrasound applications. the tgc amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy. figure 76 through figure 78 are schematics of a dual, fully differential system using the ad8332 and ad9238 12-bit high speed adc with conversion speeds as high as 65 msps. in this example, the vga outputs are dc-coupled, using the reference output of the adc and a level shifter to center the common- mode output voltage to match that of the converter. consult the data sheet of the converter to determine whether external cmv biasing is required. ac coupling is recommended if the cmv of the vga and adc are widely disparate. using the circuit shown, and a high speed adc fifo evaluation kit connected to a laptop pc, an fft can be performed on the ad8332. with the on-board clock of 20 mhz, and minimal low-pass filtering, and both channels driven with a 1 mhz filtered sine wave, the thd is C75 db, noise floor C93 db and hd2 C83 db.
ad8331/ad8332 rev. c | page 27 of 32 tb1 +5v tb2 gnd c46 1 f +5vlna +5vga l7 120nh fb l6 120nh fb tp4 (black) tp3 (red) voh1 21 25 vin1 lon1 c78 1nf c58 0.1 f 17 ad8332aru v in +a 1 lmd2 c49 0.1 f 2 inh2 c80 22pf 3 vps2 cfb1 18nf c59 0.1 f c41 0.1 f c74 1nf 4 lon2 7 5 vip2 lop2 c53 0.1 f vps1 26 com2 6 com1 23 8 vin2 c51 0.1 f 27 inh1 s1 e in1 c60 0.1 f c79 22 pf l13 120nh fb tp6 28 lmd1 c70 0.1 f com 14 9 vcm2 c48 0.1 f 10 gain c83 1nf 11 clmp r3 (r clmp ) c54 0.1 f voh2 12 v in +b c55 0.1 f vol2 13 jp12 vpsv 15 c45 0.1 f c85 1nf vol1 c56 0.1 f 16 l8 120nf fb 18 enb +5vga 19 hilo 20 vcm1 c43 0.1 f c77 1nf 22 24 vip1 lop1 +5vlna vcm1 0.1 f ad8541 vcm r22 1k ? r23 2k ? 7 6 3 2 100 ? rfb1 274 ? rfb2 274 ? vref c50 0.1 f s3 e in2 l12 120nh fb tp5 cfb2 18nf c71 1nf c68 1nf c69 0.1 f r27 100 ? l11 120nh fb jp8 dc2h l10 120nh fb jp7 dc2l r26 +5vga enable hi gain disable lo gain l9 120nh fb r24 100 ? jp9 jp10 jp17 tp2 gain jp5 in2 jp6 in1 tp7 gnd l17 sat l18 sat l19 sat l20 sat c67 sat c66 sat l1 sat l14 sat l15 sat l16 sat c64 sat c65 sat optional 4-pole low-pass filter optional 4-pole low-pass filter jp14 jp13 vcm1 4 +5vga jp10 jp16 r25 100 ? + +5vlna +5v v in ?b c42 0.1 f v in ?a 03199-c-076 figure 76. schematic, tgc, vga section
ad8331/ad8332 rev. c | page 28 of 32 vref vin+_a vin ?_a vin ?_b vin+_b mux_select 1 2 3 17 avdd 62 shared_ref 6 7 reft_a refb_a sense 11 10 reft_b refb_b 14 15 clk_a 18 clk_b 63 dcs 19 dfs 20 pdwn_b pdwn_a 60 21 oeb_b 22 16 4 13 agnd agnd 64 12 5 avdd avdd avdd 8 9 agnd agnd d5_b d4_b d3_b drgnd d2_b d1_b d0_b dnc dnc 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 drvdd d10_a d11_a otra_a d11_a(msb) drgnd d8_a drvdd d7_a d6_a d5_a d4_a d3_a d2_a d1_a d0_a drvdd d10_a drgnd otrb_b 61 d9_a 59 58 57 56 55 54 53 otr_a u1 a/d converter ad9238 d9_a d8_a d6_a d7_a d5_a d4_a d3_a d2_a d1_a d0_a dnc dnc d4_b d3_b d2_b d1_b d0_b dnc dnc otr_b d11_b d10_b d9_b d8_b d7_b d6_b d5_b 20mhz adclk +3.3vclk adclk +3.3vavdd v in ?b v in +b + +3.3vaddig sg-636pce 1 4 3 2 u5 74vhc04 + + tp 9 tp 12 4 312 12 13 10 11 u5 74vhc04 u5 74vhc04 u5 74vhc04 u5 74vhc04 u5 74vhc04 spares 8 9 6 5 tp 13 jp 1 3 2 1 v dd out gnd oe jp 4 s2 ext clock + jp 11 jp 3 jp 2 shared ref +3.3vaddig y d10_b d9_b d8_b d7_b d6_b d11_b(msb) dnc dnc oeb_a ext int v in +_a v in ?_a n data clk vref c11 10 f 6.3v c14 0.1 f c23 0.1 f c25 1nf r14 4.7k ? r11 100 ? r10 0 ? r15 0 ? c22 0.1 f c21 1nf c86 0.1 f c47 10 f 6.3v adclk c2 10 f 6.3v c18 1nf c17 0.1 f c52 10nf c57 10nf c61 18pf c40 0.1 f r5 33 ? r6 33 ? r4 1.5k ? r12 1.5k ? 1.5k ? 1.5k ? c12 10 f 6.3v r9 0 ? r8 33 ? r7 33 ? c19 1nf c20 0.1 f c63 0.1 f c26 0.1 f c24 1nf c33 10 f 6.3v c38 0.1 f c16 0.1 f c62 18pf c15 1nf c35 0.1 f c36 0.1 f c37 0.1 f r20 4.7k ? r17 49.9 ? r41 4.7k ? +3.3vclk r19 499 ? r16 5k ? r18 499 ? + +3.3vaddig 3 2 1 c32 0.1 f c39 10 f c34 10 f 6.3v c44 1 f c31 0.1 f c30 0.1 f c29 0.1 f c1 0.1 f out vr1 adp3339 akc-3.3 l2 120nh fb l3 120nh fb l4 120nh fb l5 120nh fb in out gnd 31 2 tab + +5v 03199-c-077 c13 1nf +3.3vclk +3.3vaddig +3.3vavdd +3.3vdvdd u6 figure 77. converter schematic
ad8331/ad8332 rev. c | page 29 of 32 19 1 d10_a d11_a 24 39 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 ++ 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 2 3 6 7 10 4 5 8 9 17 11 14 15 18 20 16 13 12 37 21 26 25 30 22 23 28 27 35 29 34 33 38 40 36 31 32 r39 22 ? dataclka otr_a d9_a d8_a d6_a d7_a d5_a d4_a d3_a d2_a d1_a d0_a dnc dnc otr_b d11_b d10_b d9_b d8_b d7_b d6_b d5_b d4_b d3_b d2_b d1_b d0_b dnc dnc +3.3vdvdd +3.3vdvdd +3.3vdvdd dataclk u3 74vhc541 u10 74vhc541 u7 74vhc541 u2 74vhc541 sam080upm 76 61 79 58 41 80 77 73 72 78 75 74 71 63 69 68 65 64 62 66 67 70 43 59 56 55 52 60 57 54 53 45 51 48 47 44 42 46 49 50 sam080upm rp 9 18 7 6 5 4 3 2 18 7 6 5 4 3 2 1 8 7 6 5 4 3 2 18 7 6 5 4 3 2 18 7 6 5 4 3 2 18 7 6 5 4 3 2 7 6 5 4 3 2 18 7 6 5 4 3 2 rp 11 rp 12 rp 13 rp 14 18 rp 15 rp 16 r40 22 ? 18 7 6 5 4 3 2 rp 1 18 7 6 5 4 3 2 rp2 18 7 6 5 4 3 2 rp 3 18 7 6 5 4 3 2 rp 4 18 7 6 5 4 3 2 rp 5 1 8 7 6 5 4 3 2 rp 6 18 7 6 5 4 3 2 rp 7 18 7 6 5 4 3 2 rp 8 22 4 22 4 rp 10 22 4 22 4 22 4 22 4 22 4 22 4 header up male no shroud header up male no shroud c3 0.1 f c28 10 f 6.3v c8 0.1 f c10 0.1 f c76 10 f 6.3v c7 0.1 f c9 0.1 f c27 10 f 6.3v c4 0.1 f c5 0.1 f c6 0.1 f c75 10 f 6.3v +3.3vdvdd 22 4 22 4 22 4 22 4 22 4 22 4 22 4 22 4 03199-b-078 figure 78. interface schematic
ad8331/ad8332 rev. c | page 30 of 32 pin configuration and fu nction descriptions ad8331 mode rclmp vip gain vin lop coml lmd lon vpsl inh comm voh enbv vcm vpos vol hilo enbl comm 03199-c-079 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pin 1 identifier ad8331 top view (not to scale) figure 79. 20-lead qsop table 5. 20Clead qsop (rq package) pin no. name description 1 lmd lna signal ground 2 inh lna input 3 vpsl lna 5v supply 4 lon lna inverting output 5 lop lna noninverting output 6 coml lna ground 7 vip vga noninverting input 8 vin vga inverting input 9 mode gain slope logic input 10 gain gain control voltage 11 vcm common-mode voltage 12 clmp output clamping level 13 hilo gain range select (hi or lo) 14 vpos vga 5 v supply 15 voh noninverting vga output 16 vol inverting vga output 17 comm vga ground 18 enbv vga enable 19 enbl lna enable 20 comm vga ground
ad8331/ad8332 rev. c | page 31 of 32 ad8332 com1 lop1 lmd1 lon1 vps1 inh1 voh1 enb vip1 vcm1 vin1 vpsv vol1 hilo vcm2 rclmp comm vol2 voh2 vip2 gain vin2 lop2 com2 lmd2 lon2 vps2 inh2 03199-b-081 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin 1 identifier ad8332 top view (not to scale) figure 80. 28-lead tssop table 6. 28Clead tssop (ar package) pin no. name description 1 lmd2 ch2 lna signal ground 2 inh2 ch2 lna input 3 vps2 ch2 supply lna 5 v 4 lon2 ch2 lna inverting output 5 lop2 ch2 lna noninverting output 6 com2 ch2 lna ground 7 vip2 ch2 vga noninverting input 8 vin2 ch2 vga inverting input 9 vcm2 ch2 common-mode voltage 10 gain gain control voltage 11 rclmp output clamping resistor 12 voh2 ch2 noninverting vga output 13 vol2 ch2 inverting vga output 14 comm vga ground (both channels) 15 vpsv vga supply 5 v (both channels) 16 vol1 ch1 inverting vga output 17 voh1 ch1 noninverting vga output 18 enb enablevga/lna 19 hilo vga gain range select (hi or lo) 20 vcm1 ch1 common-mode voltage 21 vin1 ch1 vga inverting input 22 vip1 ch1 vga noninverting input 23 com1 ch1 lna ground 24 lop1 ch1 lna noninverting output 25 lon1 ch1 lna inverting output 26 vps1 ch1 lna supply 5 v 27 inh1 ch1 lna input 28 lmd1 ch1 lna signal ground ad8332 top view (not to scale) lmd2 lon2 vps2 inh2 lmd1 lon1 vps1 inh1 vip2 vin2 lop2 com2 14 13 9 12 11 10 rclmp gain 15 16 vcm2 mode comm vol2 voh2 20 17 18 19 voh1 vol1 21 22 23 24 nc vpsv comm 29 30 31 32 28 25 26 27 com1 lop1 vip1 vin1 hilo enbl vcm1 enbv 03199-c-082 1 2 3 4 5 6 7 8 pin 1 indicator figure 81. 32-lead lfcsp table 7. 32Clead lfcsp (ac package) pin no. name description 1 lon1 ch1 lna inverting output 2 vps1 ch1 lna supply 5 v 3 inh1 ch1 lna input 4 lmd1 ch1 lna signal ground 5 lmd2 ch2 lna signal ground 6 inh2 ch2 lna input 7 vps2 ch2 lna supply 5 v 8 lon2 ch2 lna inverting output 9 lop2 ch2 lna noninverting output 10 com2 ch2 lna ground 11 vip2 ch2 vga noninverting input 12 vin2 ch2 vga inverting input 13 vcm2 ch2 common-mode voltage 14 mode gain slope logic input 15 gain gain control voltage 16 rclmp output clamping level input 17 comm vga ground 18 voh2 ch2 noninverting vga output 19 vol2 ch2 inverting vga output 20 nc not connected 21 vpsv vga supply 5 v 22 vol1 ch1 inverting vga output 23 voh1 ch1 noninverting vga output 24 comm vga ground 25 enbv vga enable 26 enbl lna enable 27 hilo vga gain range select (hi or lo) 28 vcm1 ch1 common-mode voltage 29 vin1 ch1 vga inverting input 30 vip1 ch1 vga noninverting input 31 com1 ch1 lna ground 32 lop1 ch1 lna noninverting output
ad8331/ad8332 rev. c | page 32 of 32 outline dimensions 28 15 14 1 8 0 compliant to jedec standards mo-153ae seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 82. 28-lead thin shrink sm all outline package [tssop] (ru-28) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 bottom view 0.50 0.40 0.30 3.50 ref 0.50 bsc 3.25 3.10 sq 2.95 0.60 max 0.60 max 0.25 min top view pin 1 indicator pin 1 indicator 5.00 bsc sq 4.75 bsc sq figure 83. 32-lead frame chip scale package [lfcsp] (cp-32) dimensions shown in millimeters 20 11 10 1 pin 1 8 0 0.236 bsc 0.154 bsc 0.010 0.004 0.012 0.008 0.025 bsc c oplanarit y 0.004 0.065 0.049 0.069 0.053 seating plane 0.010 0.006 0.050 0.016 0.341 bsc compliant to jedec standards mo-137ad figure 84. 20 lead shrink outline [qsop] (rq-20) dimensions shown in millimeters ordering guide ad8331/ad8332 models temperature range package description package outline ad8331arq C40c to +85c shrink small outlin e package 150 mil body, 25 mil pitch rq-20 ad8331arq-reel C40c to +85c shrink small outl ine package 150 mil body, 25 mil pitch rq-20 ad8331arq-reel7 C40c to +85c shrink small ou tline package 150 mil body, 25 mil pitch rq-20 AD8331-EVAL evaluation board with ad8331arq ad8332aru C40c to +85c thin shrink small outline package (tssop) ru-28 ad8332aru-reel C40c to +85c thin shrink small outline package (tssop) ru-28 ad8332aru-reel7 C40c to +85c thin shri nk small outline package (tssop) ru-28 ad8332acp-reel C40c to +85c lead frame chip scale package (lfcsp) cp-32 ad8332acp-reel7 C40c to +85c lead fra me chip scale package (lfcsp) cp-32 ad8332-eval evaluation board with ad8332aru ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the pr operty of their respective owners. c03199-0-11/03(c)

▲Up To Search▲

Price & Availability of AD8331-EVAL

	To Download AD8331-EVAL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .